Communication and memory peripherals can have hosts that communicate with multiple slaves or endpoints using chip-select. These peripherals have a common host port for a central processing unit (CPU) or direct memory access (DMA) controller and a common line interface for address and data, but data transfers happen between hosts (CPU/DMA) and multiple endpoints (slaves) through chip selects. One issue faced in this architecture is ensuring the data integrity of transfers for each endpoint while using a small area and simple user interfaces for the transfers.
In one prior art implementation, each endpoint has a dedicated First-In First-Out (FIFO) buffer or queue, but a common host/line interface. The host accesses the FIFOs through a common FIFO data register using multiplexor/demultiplexor logic.
In a second prior art implementation, a common buffer or FIFO is used for all endpoints, restricting the number of active transfers at a given time. Using dedicated FIFOs would require additional buffer area whereas using a common FIFO, the host must choose to A) track an ongoing transaction to completion before starting a transaction for a next endpoint, B) manage mechanisms to perform predefined sequence and fixed buffer utilization patterns across endpoints or C) build a sequencer to transfer controls across slaves to resume operations when the slave is next selected. Option A reduces the throughput, so that the slowest endpoint affects the operation of other endpoints, as well as host execution. Options B and C can involve complicated programming to run properly and are difficult to scale.